As integrated semiconductor devices continue to grow in complexity, there is a constant need to increase the density of the semiconductor devices. This increase in density creates several problems that can cause device failures if not addressed. Once such problem is the propensity for semiconductor devices, particularly CMOS devices, to “latch-up”. Latch-up is a well known problem caused by unwanted transistor action between elements of the integrated circuit. This unwanted transistor action can be triggered by a wide variety of events, and can cause the semiconductor device to fail.
Latch-up is generally caused by the close proximity of n-channel and p-channel devices in modern CMOS devices. For example, a typical CMOS device fabricated on a p-type substrate would contain a p-channel device fabricated in an n-well and an n-channel device fabricated in a p-well, with only a short distance between the wells. The short distance between the wells is referred to as the junction. A junction is formed when the dopant concentration in the substrate changes from an acceptor concentration (i.e. p-well) to a donor concentration (i.e. n-well). This structure inherently forms a parasitic bipolar NPN structure and parasitic PNP bipolar structure. Under certain biasing conditions the PNP structure can supply base current to the NPN structure (or vice versa), causing a large current to flow from the PNPN anode to cathode. When a PNPN device triggers, the PNPN undergoes a transition from a low current/high voltage state to a low voltage/high current state. In some cases, the low voltage/high current state can lead to thermal runaway and destruction of the elements involved in the formation of the PNPN parasitic device.
Thus, there is a need for improved methods for increasing the latch-up immunity of CMOS devices that will allow for further device scaling and increased device density.